1. Technical Field
The present invention relates, generally, to line driver amplifiers and, more particularly, to output stage coupling circuits for line driver amplifiers employing dual-drive couplings.
2. Background Art and Technical Problems
The output stage of an amplifier provides a low output resistance that enables output signal delivery to a load with minimal loss of gain. While it is the primary function of the output stage to generate the output signal with minimal loss, it is also desirable to efficiently produce the output signal with minimal total harmonic distortion (THD). This implies that the power dissipated by the output stage is minimized, while providing suitable device linearity.
The linearity of an amplifier employing negative feedback is determined by the open loop linearity of the amplifier and the cumulative loop gain around the distortion elements of the amplifier. Improving the open loop linearity generally improves amplifier performance, and may be achieved by increasing the device sizes of the output stage. In output stage amplifiers employing complimentary pull up and pull down output devices, the output stage device sizes are limited in part by the need to maintain consistent signal path gains to the output devices to both minimize distortion and maximize bandwidth. Presently known drive coupling topologies, however, do not adequately address the need for larger device sizes while also ensuring matched signal gains within the output device signal paths.
For example, the large gate capacitance of PMOS output devices and the resistive isolation of the biasing elements separating the NMOS gate node and the PMOS gate node results in output signal propagation delay. This has been addressed in some prior art systems by capacitively coupling the signal across the bias devices. This technique is a simple solution to circumventing delay incurred in the signal path through the bias devices. However, the capacitive feed-forward path is subject to a capacitive divider gain loss due to the large PMOS gate capacitance, which diminishes the usefulness of the capacitive coupling technique. For a broader discussion of capacitive coupling solutions, see: Babanezhad, J. N., xe2x80x9cA 100 MHZ, 50 xcexa9-45 dB Distortion 3.3 V CMOS Line Driver for Ethernet and Fast Ethernet Networking Applicationxe2x80x9d, IEEE International Symposium on Solid-State Circuits, 1998, paper 20.2-1, the entire contents of which are hereby incorporated by this reference.
A dual-drive coupling mechanism is thus needed which overcomes the shortcomings of the prior art.
The present invention is directed to an output stage for an amplifier that satisfies these needs. An output stage having features of the present invention includes a PMOS output device coupled to an NMOS output device. Two signal sources are present, one coupled to the PMOS output device and one coupled to the NMOS output device. A floating resistor network is also present, coupled between the two signal sources.
An output stage according to the present invention may operate as follows: the input to the output stage is provided through one of two NMOS signal sources. A PMOS output device is coupled to an NMOS output device. Both output devices are a biased by a separate current source and a floating resistor network. The output at the junction of the PMOS and NMOS output device is the output of the output stage.